Memory cell of nonvolatile semiconductor memory device

ABSTRACT

The current paths of a plurality of floating gate type MOSFETs are series-connected to form a series circuit. The series circuit is connected at one end to receive a reference voltage, and is connected to data programming and readout circuit. In the data programming mode, electrons are discharged from the floating gate to the drain of the HOSFET or holes are injected into the drain into the floating gate. The data readout operation is effected by checking whether current flows from the other end to the one end of the series circuit or not.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] This invention relates to a nonvolatile semiconductor memorydevice having floating gate type MOSFETs as memory cells.

[0003] 2. Description of the Related Art

[0004] Conventionally, EEPROM and UVEPROM are known as the nonvolatilesemiconductor memory device with a floating gate structure, for example.In the EEPROM, data is electrically written in or programmed andelectrically erased. With a memory cell in the EEPROM, data can beprogrammed by injecting or emitting electrons into or from the floatinggate via an oxide film with a thickness of approx. 100 Å which isextremely thinner than a gate oxide film by use of the tunnel effect.The EEPROM is explained in detail in U.S. Pat. No. 4,203,158(Frohman-Bentchkowsky et al. “ELECTRICALLY PROGRAMMABLE AND ERASABLE MOSFLOATING GATE MEMORY DEVICE EMPLOYING TUNNELING AND METHOD OFFABRICATING SAME”).

[0005] However, since, in the above EEPROM, two transistors are used toconstitute a single memory cell, the memory cell size becomes large andthe chip cost will increase.

[0006] For the above reason, ultraviolet erasable non-volatilesemiconductor memory devices or UVEPROM has an advantage in attaininghigh integration density, in which each memory cell is formed of asingle transistor. In the UVEPROM, data can be electrically programmedand erased by applying ultraviolet rays thereto. As described above, inthe UVEPROM, each memory cell is formed of a single transistor so thatthe chip size can be reduced for the same memory scale or capacity asthat of the EEPROM.

[0007] However, in the UVEPROM, a high power source voltage is requiredto program data. That is, in order to inject electrons into the floatinggate of a selected memory cell, a high voltage is applied between thecontrol gate and drain to cause impact ionization in an area near thedrain region, injecting the electrons thus generated into the floatinggate. For this purpose, it becomes necessary to provide a power sourceof high voltage for data programming outside the memory device. Incontrast, since electrons are injected into or emitted from the floatinggate by the tunnel effect in the EEPROM, it is not necessary to use sucha programming power source as is used in the UVEPROM and data can beprogrammed by an output voltage of a booster circuit provided in thesame chip as that of the memory device. Therefore, the EEPROM can beoperated on a single power source voltage of 5 V.

[0008] As described above, the UVEPROM can be formed at a higherintegration density in comparison with the EEPROM. However, in general,since a single contact portion is formed for each common drain of twomemory cell transistors, the number of contact portions increases.Increase in the number of contact portions is an obstruction to theattainment of high integration and large memory capacity. For thisreason, the UVEPROM can be formed at a higher integration density thanthe EEPROM, but can be further improved in its integration density.

SUMMARY OF THE INVENTION

[0009] An object of this invention is to provide an EEPROM in which datacan be electrically programmed, the memory cell size can be reduced andthe cost can be lowered.

[0010] Another object of this invention is to provide a UVEPROM in whichthe number of contact portions can be reduced to further reduce the chipsize and the high integration density and low cost can be attained.

[0011] According to one embodiment of this invention, there is provideda nonvolatile semic-nductor memory device which comprises a selectiontransistor which is connected at one end to a column line and whose gateis connected to a row line; and a plurality of cell transistors whichare connected in series between the other end of the selectiontransistor and a reference potential and whose control gates areconnected to row lines, wherein electrons are emitted from a floatinggate to a drain of the cell transistor or holes are injected from thedrain to the floating gate in the data programming mode.

[0012] In a first embodiment of this invention, there is provided anEEPROM in which the selection transistor can be commonly used for thecell transistors so that the memory cell can be formed of substantiallyone cell transistor. Therefore, the size of the memory cell can bereduced, and the high integration density and low cost can be attained.

[0013] In a second embodiment of this invention, there is provided aUVEPROM in which a single contact portion can be commonly used for threeor more cell transistors, thereby reducing the number of contactportions. Thus, the high integration density and low cost can beattained.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014]FIG. 1 is a circuit diagram showing a nonvolatile semiconductormemory device according to a first embodiment of this invention;

[0015]FIGS. 2 and 3 are timing charts for illustrating the operation ofthe circuit shown in FIG. 1;

[0016]FIG. 4A is a pattern plan view showing the construction of a celltransistor in the circuit of FIG. 1;

[0017]FIG. 4B is a cross sectional view taken along line X-X′ of thepattern plan view of FIG. 4A;

[0018]FIG. 4C is a cross sectional view taken along line Y-Y, of thepattern plan view of FIG. 4A;

[0019]FIG. 5A is a pattern plan view showing another construction of acell transistor in the circuit of FIG. 1;

[0020]FIG. 5B is a cross sectional view taken along line Y-Y′ of thepattern plan view of FIG. 5A;

[0021]FIG. 6A is a pattern plan view showing still another constructionof a cell transistor in the circuit of FIG. 1;

[0022]FIG. 6B is a cross sectional view taken along line X-X′ of thepattern plan view of FIG. 6A;

[0023]FIG. 7 is a circuit diagram showing another construction of a dataprogramming circuit constituted by two MOSFETs and a data input circuitin the circuit of FIG. 1;

[0024]FIG. 8 is a circuit diagram showing still another construction ofa data programming circuit constituted by two MOSFETs and a data inputcircuit in the circuit of FIG. 1;

[0025]FIG. 9 is a circuit diagram showing still another construction ofa data programming circuit constituted by two MOSFETs and a data inputcircuit in the circuit of FIG. 1;

[0026]FIG. 10 is a circuit diagram showing the construction of a memorydevice formed by arranging cell transistors shown in FIG. 1 in a matrixform;

[0027]FIGS. 11 and 12 are timing charts for illustrating operation ofthe circuit of FIG. 10;

[0028]FIGS. 13 and 14 are diagrams showing the levels of various signalsin the circuit of FIG. 10;

[0029]FIG. 15 is a circuit diagram showing the construction of a circuitfor applying a power source voltage of two different voltage levels tothe row decoder in the circuit of FIG. 10;

[0030]FIG. 16 is a circuit diagram showing a modified construction of amemory cell section in the circuit of FIG. 1;

[0031]FIG. 17 is a circuit diagram showing a modified construction of aperipheral portion of the memory cell section in the circuit of FIG. 10;

[0032]FIG. 18A is a circuit diagram for illustration of anotherconstruction of the circuit of FIG. 10;

[0033]FIG. 18B is a circuit diagram showing a construction of a boostercircuit in the circuit of FIG. 18A;

[0034]FIG. 19 is a circuit diagram for illustration of the principle ofa nonvolatile semiconductor memory device according to a secondembodiment of this invention;

[0035]FIG. 20 is a pattern plan view of the circuit of FIG. 19;

[0036]FIG. 21A is another pattern plan view of the circuit of FIG. 19;

[0037]FIG. 21B is a cross sectional view taken along line Z-Z, of thepattern plan view of FIG. 20A;

[0038]FIG. 22 is a pattern plan view indicating that the patternstructure of FIGS. 21A and 21B can be advantageously used in themanufacturing process;

[0039] FIGS. 23 to 25 and 26A are still other pattern plan views of thecircuit of FIG. 19;

[0040]FIG. 26B is a pattern plan view illustrating an ion-implantationmask used for forming the pattern of FIG. 26A;

[0041]FIG. 27 is a diagram showing the circuit model formed toillustrate the operation of the circuit of FIG. 17;

[0042]FIG. 28 is a diagram showing a voltage-current characteristic of afloating gate type MOSFET;

[0043]FIGS. 29 and 30 are timing charts for illustrating the operationof the circuit of FIG. 17;

[0044]FIG. 31 is a circuit diagram showing the construction of anonvolatile semiconductor memory device formed of memory cells of thesame construction as the memory cell shown in FIG. 19 and formed to havea plural-bit output construction;

[0045] FIGS. 32 to 34 are timing charts for illustrating the operationof the memory device of FIG. 31;

[0046]FIGS. 35 and 36 are circuit diagrams showing the detailconstruction of a row decoder in the memory device of FIG. 31;

[0047]FIG. 37 is a circuit diagram showing a modification of the circuitof FIG. 36;

[0048]FIGS. 38 and 39 are the truth tables obtained in the row decoderof the memory device of FIG. 31; and

[0049]FIG. 40 is a circuit diagram showing a modification of the circuitof FIG. 19.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0050]FIG. 1 shows a memory cell section and a peripheral circuitsection (programming circuit and readout circuit) thereof in an EEPROMaccording to a first embodiment of this invention. The FIG. 1 circuit isschematically shown for briefly explaining the first embodiment of thisinvention. Data programming circuit 10 is constituted by input circuit11 and N-channel MOSFETs 12 and 13. Output signal D1 from data inputcircuit 11 is supplied to the gate of MOSFET 12 which is connected atone end to high voltage power source Vpp. Output signal D2 of data inputcircuit 11 is supplied to the gate of HOSFET 13 connected between nodeN1 on the other end of MOSFET 12 and a ground terminal (referencepotential terminal). MOSFET 12 is used to charge node N1 in theprogramming mode and MOSFET 13 is used to discharge node N1. The currentpaths of selection transistor ST and cell transistors CT1 to CT4 areserially connected between node N1 and the ground terminal. The gate ofselection transistor ST is applied a signal X1 for selecting a group ofcell transistors CT1 to CT4. Furthers the gates of cell transistors CT1to CT4 are respectively applied signals W1 to W4 for respectivelyselecting cell transistors CT1 to CT4. Node N1 is further connected toone end of N-channel MOSFET 14 whose conduction state is controlled bysignal RE set at “1” level in the readout mode and at “0” level in theprogramming mode. The other end of MOSFET 14 is connected to an inputterminal of data detection circuit 15. P-channel MOSFET 16 is connectedbetween power source terminal vcc and node N2 which is present on theinput side of data detection circuit 15 and the gate thereof isconnected to node N2. MOSFET 16 functions as a load in the readout mode.

[0051] For brief explanation, a combination of selection transistor STand cell transistors CT1 to CT4 is referred to as a single memory cellin the first embodiment. However, it should be understood that thememory cell is different from an ordinary memory cell and can store dataof four bits (the number of bits corresponds to that of cell transistorshaving current paths connected in series). That is, the memory cell inthis example is equivalent to four conventional memory cells.

[0052] There will now be described an operation of the memory devicewith the above construction with reference to FIGS. 2 and 3. FIG. 2 is atiming chart of various signals in the programming mode in the circuitof FIG. 1. First, signal RE is set to “0” level to turn off transistor14. At time to, signals X1 and W1 to W4 are set to a high voltage levelto inject electrons into the floating gates of cell transistors CT1 toCT4. Then, at successive times t1 to t4, signals W4 to W1 aresequentially set to 0 V in this order. If output signals D1 and D2 ofdata input circuit 11 are respectively set at “1” and “0” levels whensignals W1 to W4 are set to 0 V, transistors 12 and 13 are respectivelyturned on and off, causing a high voltage from high voltage power sourcevpp to be applied to the drain of a corresponding transistor viatransistor 12 and selection transistor ST so that electrons can beemitted from the floating gate of the respective cell transistors. InFIG. 2, since signal D1 is set at “1” when signals W3 and W1 are set to0 VA electrons are emitted from the floating gates of cell transistorsCT3 and CT1. Thus, data can be programmed. In a case where outputsignals D1 and D2 of data input circuit 11 are set at “0” and “1”levels, respectively, node N1 is discharged.

[0053] In the data readout mode, output signals D1 and D2 of data inputcircuit 11 are set to “0” level to turn off transistors 12 and 13.Further, signals RE and X1 are set to “1” level and the control gatevoltage of a cell transistor to be selected for data readout is set to 0V. At this time, the control gate voltages of other cell transistors areset to “1” level. FIG. 3 is a timing chart showing the case where datais sequentially read out from cell transistors CT4 to CT1. Morespecifically, data is read out from cell transistor CT4 in a period oftime t0 to t1, from cell transistor CT3 in a period of time t1 to t2,from cell transistor CT2 in a period of time t2 to t3, and from celltransistor CT1 in a period of time t3 to t4. Assume now that signal W1is set at 0 v and signals W2 to W4 are set at “1” level. Then, data isread out from cell transistor CT1. If data has been programmed asdescribed before, the threshold voltage thereof is set negative sinceelectrons have been emitted from the floating gate of cell transistorCT1, and therefore cell transistor CT1 is turned on by signal W1 of 0 V.The control gate voltages of other cell transistors CT2 to CT4 are setat “11” level and the cell transistors are turned on. Thus, all the celltransistors are set in the conductive state, lowering the potential ofnode N2. The potential fall is detected by means of data detectioncircuit 15 and thus data can be read out from cell transistor CT1.Assume now that signal W2 is set to 0 V to select cell transistor CT2and electrons are kept held in the floating gate of cell transistor CT2.Since, in this case, the control gate voltage is set at 0 V, celltransistor CT2 is turned off. Therefore, node N2 is charged viatransistor 16, and the potential rise of node N2 is detected by means ofdata detection circuit 15. It should be noted here that the thresholdvoltages of cell transistors CT1 to CT4 having electrons kept held inthe floating gates are so determined that the cell transistors can beturned on when the control gate voltages thereof are set to “11” level.

[0054]FIGS. 4A to 4C show an example of a transistor which is suitablefor cell transistors CT1 to CT4 and in which part of the insulation filmon the channel region is formed of a thin oxide film with the thicknessof approx. 100 Å. FIG. 4A is a pattern plan view, FIG. 4B is a crosssectional view taken along line X-X′ of FIG. 4A, and FIG. 4C is a crosssectional view taken along line Y-Y′ of FIG. 4A. N⁺−type source anddrain regions (18 and 19) are formed with a predetermined distancetherebetween in the main surface area of P-type silicon substrate 17.First oxide film 20 having thin portion 20A is formed on that part ofsemiconductor substrate 17 which lies on the channel region betweensource and drain regions (18 and 19). Floating gate 21 is formed onoxide film 20, and control gate 23 is formed on second oxide film 22formed on floating gate 21.

[0055]FIGS. 5A and 5B show another example of a transistor suitable forcell transistors CT1 to CT4 in the circuit of FIG. 1. In this case, aninsulation layer disposed on the entire portion of the channel region isformed of an oxide film with a thickness of approx. 100 Å. Portions inFIGS. 5A and 5B which are similar to those in FIGS. 4A to 4C are denotedby the same reference numerals. FIG. 5A is a pattern plan view and FIG.5B is a cross sectional view taken along line of Y-Y′ of FIG. 5A.

[0056]FIGS. 6A and 6B show still another example of a transistorsuitable for cell transistors CT1 to CT4 in the circuit of FIG. 1. Inthe cell transistor shown in FIGS. 6A and 6B, N⁻−type impurity region 24with low impurity concentration is formed in part of the channel region.That is, the cell transistor is a depletion type transistor. FIG. 6A isa pattern plan view and FIG. 6B is a cross sectional view taken alongline of X-X′ of FIG. 6A. With this construction, even if electrons areinjected into the floating gate to such an extent that the celltransistor may be kept off when a “1” level signal is supplied to thecontrol gate, current will flow since source and drain regions 18 and 19are connected to each other via N⁻−type impurity region 24. Theoperation of reading out data from the cell transistor with aboveconstruction is effected by detecting the amount of current varyingaccording to whether or not electrons are injected into the floatinggate when a “0” level voltage is applied to the control gate.

[0057]FIG. 7 shows another construction of data programming circuit 10constituted by MOSFETs 12 and 13 and data input circuit 11 in thecircuit of FIG. 1. Programming data Din is supplied to CMOS inverter 27formed of P-channel MOSFET 25 and N-channel HOSFET 26. The outputterminal of CMOS inverter 27 is connected to one end of N-channel MOSFET28 whose gate is connected to power source Vcc. P-channel MOSFET 29 isconnected between the other end of MOSFET 28 and power source Vpp ofhigh voltage, for example, 12.5 V. Further, the other end of MOSFET 28is connected to the gates of P-channel MOSFET 30 and N-channel MOSFET31. One end of MOSFET 30 is connected to power source Vpp, and the otherend thereof is connected to one end of MOSFET 31. N-channel MOSFET 32 isconnected between the other end of MOSFET 31 and the ground terminal.The gate of MOSFET 32 is connected to the other end of MOSFET 31. Aconnection node between MOSFETs 30 and 31 is connected to the gate ofMOSFET 29 and one end of N-channel MOSFET 33. The gate of MOSFET 33 issupplied with signal PR which is set at an “1” level in the program modeand an “0” level in the readout mode. In this case, “1” level indicatesa high voltage level approximately equal to Vpp level. If signal PR isset higher than Vpp by the threshold voltage of MOSFET 33, voltage ofVpp is transmitted as it is to mode N1. The other end of MOSFET 33 isconnected to node N1 or one end of selection transistor ST and one endof transistor 14 in the circuit of FIG. 1.

[0058] With the above construction, signal PR is set at “1” level in thedata programming mode to turn on MOSFET 33. In this case, high voltageVpp is generated from data programming circuit 10 when input data Din isat “1” level, and a signal of a level equal to threshold voltage V_(TH)of MOSFET 32 is generated as programming data when input data Din is at“0” level. In this example, a signal of V_(TH) level is generated wheninput data Din is at “0” level. The reason why a V_(TH) level signal isoutput when input data Din is at “0” level is as follows:

[0059] As will be described later, a plurality of memory cells as shownin FIG. 1 are arranged in a matrix form in order to from an integratedcircuit. Therefore, adjacent transistors ST are controlled by the samesignal X1, and the gates of transistors ST are formed of the samepolysilicon layer, for example. Signal X1 is set at a high voltage levelin the programming mode, and at this time, potentials of the drains oftransistors ST are set at different levels according to the programmingdata. For example, in a case where electrons are emitted from thefloating gate of a cell transistor connected to a first one oftransistors ST and electrons are injected into the floating gate of acell transistor connected to the other or second transistor ST, thedrain of the first transistor ST is set at a high potential and thedrain of the second transistor ST is set at a low potential. In thiscase, a parasitic MOS transistor is formed between the first and secondtransistors ST connected to the same polysilicon layer. If the parasiticMOS transistor has a threshold voltage lower than the potential level ofsignal X1, unwanted current will flow from the first transistor ST whosedrain is set at a high potential to the second transistor ST through theparasitic MOS transistor. The drain potential of the first transistor STis lowered by the unwanted current flow, deteriorating the programmingcharacteristics. In order to prevent the deterioration of theprogramming characteristics, the amount of impurity implanted into thefield area for channel-cut may be increased to get a high thresholdvoltage of the parasitic MOS transistor. However, if the impurityconcentration of the field area is increased, the breakdown voltage inthe drain region to which a high voltage is applied will be lowered. Asshown in FIG. 7, if the drain of transistor ST which is set at a lowpotential to inject electrons into the floating gate is connected to theground terminal through MOSFET 32, the above-described problem will notoccur. When current flows through the parasitic MOS transistor, thedrain of the second transistor ST is charged and the drain voltage isincreased, thus increasing the source potential of the parasitic MOStransistor. The source potential increase of the parasitic MOStransistor being on the increase of the threshold voltage withoutincreasing the amount of impurity implanted into the field area forchannel-cut. Therefore, no current will flow from the first transistorST to the second transistor ST through the parasitic MOS transistor andthe drain voltage of the first transistor ST can be enhanced to asufficiently high voltage level, effectively preventing thedeterioration of the programming characteristics. In the data readoutmode, since signal PR is set at “0” level to turn off MOSFET 33, dataprogramming circuit 10 has no influence on the potential at node N1.

[0060]FIG. 8 shows still another construction of data programmingcircuit 10 in the circuit of FIG. 1. In the circuit, depletion typeMOSFET 34 is used as a load instead of P-channel MOSFET 30 in FIG. 7.Further, in the circuit, a plurality of diode connected MOSFETs 32-1 to32-n are provided. The number of MOSFETs 32-1 to 32-n is determined by adesigned output level. With this construction, substantially the sameoperation as that of the FIG. 7 can be attained.

[0061] As described above, in order to prevent current from flowingthrough the parasitic MOS transistor, it is preferable to set higher thepotential of an area acting as the source of the parasitic MOStransistor into which the current flows. when the source potential isset higher, we get a higher threshold voltage of the parasitic MOStransistor. For this reason, as shown in FIG. 8, a plurality of MOSFETs32-1 to 32-n are used. However, in this case, if the source potential isset to be extremely high, electrons may happen to be emitted from thedrain to the floating gate of the cell transistor. Therefore, it isnecessary to set the source potential in such a potential level thatelectrons will not emitted from the drain of the cell transistor andcurrent will not flow out from the parasitic MOS transistor.

[0062]FIG. 9 shows still another construction of data programmingcircuit 10 in the circuit of FIG. 1. Inverted signal {overscore (Din)}of data Din is supplied to the gates of P-channel MOSFET 35 andN-channel MOSFET 36. P-channel MOSFET 37 is connected between one end ofMOSFET 35 and power source Vcc. The gate of MOSFET 37 is supplied withsignal {overscore (PR)} which is set at “L” level in the program mode.The other end of MOSFET 35 is connected to one end of MOSFET 36 which isconnected at the other end to the ground terminal. N-channel MOSFET 38having a gate supplied with signal {overscore (PR)} is connected betweenthe ground terminal and a connection node between KOSFETs 35 and 36.Further, one end of N-channel MCSFET 39 whose gate is connected to powersource Vcc is connected to a connection node between MOSFETs 35 and 36.P-channel MOSFET 40 is connected between the other end of MOSFET 39 andpower source Vpp. The other end of MOSFET 39 is connected to the gatesof P-channel MOSFET 41 and N-channel MOSFET 42. One end of MOSFET 41 isconnected to power source Vpp and the other end thereof is connected toone end of MOSFET 42 which is connected at the other end to the groundterminal. The gates of MOSFET 40 and P-channel MOSFET 43 are connectedto a connection node between MOSFETs 41 and 42. One end of MOSFET 43 isconnected to power source Vpp and the other end thereof is connected toone end of N-channel MOSFET 44. Diode connected N-channel MOSFET 45 isconnected between the other end of MOSFET 44 and the ground terminal.

[0063] Data {overscore (Din)} is supplied to an input terminal of CMOSinverter 48 including P-channel MOSFET 46 and N-channel MOSFET 47. Anoutput signal of CMOS inverter 48 is supplied to the gates of P-channelMOSFET 49 and N-channel MOSFET 50. P-channel MOSFET 51 is connectedbetween one end of MOSFET 49 and power source Vcc, and the gate ofMOSFET 51 is supplied with signal {overscore (PR)}. The other end ofMOSFET 49 is connected to one end of MOSFET 50 which is connected at theother end to the ground terminal. N-channel MOSFET 52 having a gatesupplied with signal {overscore (PR)} which is set at “L” level in theprogramming mode is connected between the ground terminal and aconnection node between MOSFETs 49 and 50. The gate of MOSFET 44 isconnected to a connection node between MOSFETs 49 and 50, and theconnection node between MOSFETs 43 and 44 is connected to node N1.

[0064] With this construction, the same operation as that of the circuitshown in FIGS. 7 and 8 can be attained. That is, since signal {overscore(PR)} is set at “H” level at a time other than the programming mode, forexample, in the readout mode, MOSFETs 38 and 52 are turned on andMOSFETs 37 and 51 are turned off. Therefore, MOSFETS 43 and 44 areturned off, electrically isolating data programming circuit 10 from nodeNl. In contrast, signal {overscore (PR)} is set at “0” level in the dataprogramming mode so that MOSFETs 37 and 51 will be turned on and MOSFETs38 and 52 will be turned off. Therefore, high voltage Vpp is generatedfrom data programming circuit 10 when input data {overscore (Din)} is at“0” level, and a signal at a level equal to the threshold voltage V_(TH)of MOSFET 45 when input data Din is at “1” level.

[0065]FIG. 10 shows a nonvolatile semiconductor memory device formed byarranging memory cells with the above construction in a matrix form. InFIG. 10, data programming and reading circuits 200 surrounded byone-dot-dash lines in the circuit of FIG. 1 are connected to datainput/output lines I01 to I08. In FIG. 10, a plurality of dataprogramming and reading circuits 200 are formed by a single block. Rowdecoder 53 generates signals X1, X2, . . . , signals W11, W12, . . . ,W1n, and signals W21, W22, . . . , W2n to select a row line or lines inthe memory cell array. Column decoder 54 generates signals Yl to Ym toselectively activate column selection MOSFETs Ql to Qm so that data tobe programmed can be supplied to one of memory cell blocks Bl to Bmthrough data input/output lines I01 to I08 or data can be read out fromone of the memory cell blocks through the input/output lines. Further,column decoder 55 generates signals Z2 to Zm to selectively activatedepletion type MOSFETs QD2 to QDm for array division so as tosequentially specify memory cell blocks Bl to Bm in the program mode.

[0066] With the above construction, the data programming operation iseffected starting from the memory cell which is positioned far away fromrow decoder 53. Now, the data programming operation in the memory deviceof FIG. 10 is explained. FIG. 11 is a timing chart of various signals inthe program mode. That is, the data programming operation is effectedwith respect to the memory cells connected to data line X1 of memorycell block Bm. At the time of programming, signals X1, Ym, Z2 to Zm areset at a high voltage level. In this condition, signals W11 to W1n areset to a high voltage level to inject electrons into the floating gatesof the cell transistors. Then, signals W1n to w11 are sequentially setto “0” level in this order. In this case, electrons are emitted onlywhen the control gate voltage is at “0” level and programming data issupplied as a high voltage to the drain through any one of datainput/output lines 101 to 108, column selection transistor Qm andselection transistor STm, and thus data can be programmed in therespective cell transistors.

[0067]FIG. 12 is a timing chart for the readout mode, and signals X andY associated with a selected memory cell are set at “1” level. Further,one of signals W11 to W1n associated with cell transistors of theselected memory cell is set to “0” level, and all the gate voltages ofnonselected cell transistors are set at “1” level. As a result, data canbe read out in the same manner as in the case of the circuit of FIG. 1.

[0068]FIG. 13 shows the truth table indicating the levels of signals W11to win. For simplifying the explanation, assume that n is set to 4, andthe cell transistor is selected by tow address signals A0 and A1. Inthis case, signal RE is used to identify the programming mode andreadout mode. That is, signal RE indicates the programming mode when setat “0”, and the readout mode when set at “1”.

[0069] Signal I is a signal used for initialization. If signal I is setat “1” when signal RE is set at “0” indicating the programming mode, W11to W14 are set at “1” level or a high voltage level irrespective ofsignals AO and Al, causing electrons to be injected into the floatinggates of the cell transistors connected to W11 to W14. When signals Iand RE are at “0” level, the potential levels of W11 to W14 aredetermined according to address signals AO and Al as shown in the truthtable.

[0070] When signal RE is at “1” level indicating the readout mode, thepotential levels of W11 to W14 are determined according to addresssignals AO and Al irrespective of signal I. That is, in the readoutmode, only one of W11 to W14 selected by a combination of addresssignals AO and Al is set to “0” level.

[0071] “1” level at which W11 to W14 are set in the programming mode isset at a high voltage of, for example, approx. 20 V, and “1” level atwhich W11 to W14 are set in the readout mode is set to a low voltage of,for example, 5 V.

[0072]FIG. 14 shows the truth table of signals X1, X2, W11 to W14, andW21 to W24 in the readout mode in combination with three addresses A0 toA2. In this example, if X1=“0”, signals W11 to W14 are set at “0” levelin the readout mode, but it is also possible to set one of signals W11to W14 to “0” in the same manner as in the case of X1=“1”.

[0073]FIG. 15 shows a circuit for selectively producing power sourcevoltage Vcc which set a potential used in the reading mode and highlevel voltage Vpp of 20 V, for example, which is used for programmingmode to row decoder 53 in the circuit of FIG. 10. In the circuit of FIG.15, capacitor 59 is connected between the ground terminal and an outputterminal of CMOS inverter 58 including P-channel MOSFET 56 and N-channelMOSFET 57. The output terminal of CMOS inverter 58 is connected to aninput terminal of CMOS inverter 62 including P-channel MOSFET 60 andN-channel MOSFET 61. Capacitor 63 is connected between the groundterminal and the output terminal of CMOS inverter 62. The outputterminal of CMOS inverter 62 is connected to an input terminal of CMOSinverter 66 including P-channel HOSFET 64 and N-channel MOSFET 65. Theoutput terminal of CMOs inverter 66 is connected to the input terminalof CMOS inverter 58 and one electrode of capacitor 67. N-channel MOSFET68 having a gate connected to power source Vcc is connected between theother electrode of capacitor 67 and the power source Vcc. Further, theother electrode of capacitor 67 is connected to one end and the gate ofN-channel MOSFET 69. The current paths of depletion type (D-type) MOSFET70 and N-channel MOSFET 71 are serially connected between the other endof MOSFET 69 and power source Vcc. The gate of HOSFET 70 is connected toreceive signal {overscore (PR)} and the gate of MOSFET 71 is connectedto the other end of MOSFET 69. D-type MOSFET 72 having a gate connectedto receive signal PR is connected between the other end of MOSFET 69 andhigh level voltage source Vpp. Node N3 used as an output terminal of thecircuit of FIG. 15 is connected to a power source terminal of rowdecoder 53 in the circuit of FIG. 10.

[0074] With the construction described above, when signal PR is set at“0” level and signal {overscore (PR)} is set at “1” level, or when datais read out from a cell transistor, MOSFETs 70 and 72 are turned on andoff, respectively, CMOS inverters 58, 62 and 66 are connected toconstitute a ring oscillator whose oscillation output is supplied to oneelectrode of capacitor 67. Power source voltage Vcc is stepped up bymeans of MOSFETs 68, 69 and 71, and is transmitted to node N3. The otherend of MOSFET 69 is set at a potential higher than power source voltageVcc by the threshold voltage of MOSFET 71. In contrast, when signal PRis set at “1” level and signal {overscore (PR)} is set at “0” level,that is, when data is programmed in a cell transistor, MOSFETs 72 and 70are turned on and off, respectively. Therefore, in this case, powersource voltage Vpp is supplied to node N3 through MOSFET 72.

[0075] Thus, in the circuit of FIG. 15, a first readout voltage higherthan power source voltage Vcc is supplied when data is read out from acell transistor, and power source Vpp higher than the first readoutvoltage is supplied in the programming mode. In this way, row decoder 53is operated on power source voltages of different voltage levels in thedata programming mode and readout mode.

[0076] It is of source possible to supply power source voltage Vccitself as the power source voltage for row decoder 53 in the datareadout mode. In the readout mode, the gate of the selected celltransistor is set to “0” and the gate of the nonselected cell transistoris set to “1”. Data is determined depending on whether or not currentflows in the selected cell transistor whose gate is set at “0”. As thecurrent flowing in the selected cell transistor becomes larger, datainput/output line IO may be charged or discharged at a higher speed,thus enhancing the data readout speed.

[0077] Since the memory cell is constituted by connecting celltransistors in series, the same amount of current as that which flows inthe selected cell transistor flows in the nonselected cell transistor.Therefore, current flowing in the memory cell is determined by a seriescircuit of the resistive component of the selected cell transistor andthe resistive component of the nonselected cell transistor. For thisreason, the current flowing in the memory cell becomes larger as theresistive component of the nonselected cell transistor is reduced.Therefore, in the circuit of FIG. 15, a voltage which is higher thanpower source voltage Vcc by the threshold voltage of MOSFET 71 is usedas the power source voltage for row decoder 53 so as to set the gatevoltage of the nonselected cell transistor higher, thus reducing theresistance of the nonselected cell transistor. In a case where rowdecoder 53 is constituted by CMOS circuits, current which may constantlyflow in the circuit can be suppressed to 0. Therefore, the circuit ofFIG. 15 can be satisfactorily used as a power source. Further, powersource voltage Vpp can be supplied from the exterior. However, if theperipheral circuit is formed of CMOS circuits, constantly flowingcurrent can be prevented, and therefore Vpp can be internally obtainedby stepping up power source voltage Vcc by use of a charge pump circuitin the well known manner.

[0078]FIG. 16 shows another construction of the memory cell section inFIG. 1. In the circuit of FIG. 16, N-channel MOSFET 80 whose conductionstate is controlled by signal {overscore (PR)} set at “0” or “1” levelrespectively in the programming mode or readout mode is connectedbetween cell transistor CT4 of FIG. 1 and the ground terminal. Portionsin FIG. 16 which are similar to those in FIG. 1 are denoted by the samereference numerals and the detail explanation thereof is omitted.

[0079] With this construction, even if a leakage current flows from celltransistors CT1 to CT4 when a high voltage is applied to the drainthereof in the program mode, the leakage current can be cut off by meansof transistor 80. Thus, the drain potential can be prevented from beinglowered and the programming characteristic can be prevented from beingdeteriorated. In the circuit of FIG. 10, transistor 80 can be usedcommonly for a plurality of cell blocks.

[0080]FIG. 17 shows a circuit which can be used to form the FIG. 1circuit in a matrix form. The circuit of FIG. 17 corresponds to one ofmemory cell blocks Bi to Bm, and includes MOSFETs QT1, QT2, . . . whichare connected to the control gates of the cell transistors and whoseconduction states are controlled by signals X1, X2, . . . . Sincesignals are input through MOSFETs QT1, QT2, . . . a desired one of thememory cell blocks can be programmed by selectively satisfying a logicalcondition determined by a combination of signals W11, W12, . . . andsignals Z2 to Zm supplied to corresponding memory cell blocks toselectively set signals W1n1, . . . , W121, W111 to a high voltagelevel. In this case, two-layered aluminum wiring layer is used andsignals W111, W121, W1n1 are transmitted via the second wiring aluminumlayer. Therefore, the chip size will be increased because the wiringlayer for signals W111, W121, W1n1 is additionally provided, butincrease in the chip size can be suppressed to a minimum.

[0081] Further, it is possible to connect a latch circuit shown in FIG.18 to each column line (the drain of selection transistor ST). In thiscase, one end of MOSFET 81 and input and output terminals of boostercircuit 82 are connected to each column line. The gate of MOSFET 81 isconnected to receive signal LA/PR which is set at “1” level in thelatching operation and programming mode, and set at “0” level in theread mode. The other end of MOSFET 81 is connected to an output terminalof CMOS inverter 85 constituted by P-channel MOSFET 83 and N-channelMOSFET 84 and an input terminal of CMOS inverter 88 constituted byP-channel MOSFET 86 and N-channel MOSFET 87. The input terminal of CMOSinverter 85 is connected to the output terminal of CMOS inverter 88.Thus, CMOS inverters 65 and 88 are connected to constitute latch circuit89. Data to be programmed can be latched in latch circuit 89, and thecolumn lines can be selectively set at high voltage or 0 V according tothe latched data for one row of memory cells so that the all memorycells connected to one line of row lines can be programmed. Therefore,MOSFETs QD2 to QDm for array division shown in FIG. 10 can be omitted.

[0082]FIG. 18B shows the construction of booster circuit 82 in thecircuit of FIG. 18A. Clock generating circuit 90 generates clock signal(C. The output terminal of clock generating circuit 90 is connected toone electrode of MOS capacitor 92 which is connected at the otherelectrode to one end of MOSFET 93 having a threshold of approx. 0 V andone end and the gate of MOSFET 94. The other end of MOSFET 93 isconnected to receive an output voltage Vpp′ of another booster circuit(not shown) and the gate thereof is connected to the column line. Theother output terminal of MOSFET 94 is connected to the column line.

[0083] In booster circuit 82, when the latch data is “1”, the potentialof the column line is stepped up and supplied to the cell transistor.

[0084] According to the first embodiment described above, a nonvolatilesemiconductor memory device is provided in which data can beelectrically programmed, the memory cell size can be made smaller than aUVEPROM, and the low cost can be attained.

[0085]FIG. 19 is a circuit diagram for illustrating the principle of anonvolatile semiconductor memory device according to a second embodimentof this invention. That is, the nonvolatile semiconductor memory deviceis constructed by applying this invention to a UVEPROM. Each of celltransistors MCI to MC4 is constituted by a floating gate type MOSFEThaving floating and control gates. The current paths of four celltransistors MC are serially connected to constitute series circuit 100.One end of series circuit 100, or the drain of cell transistor MC1 isconnected to programming voltage source Vpp of high voltage, forexample, 20 V through enhancement type (E-type) MOSFET 101 forapplication of programming voltage. The other end of series circuit 100or the source of cell transistor MC4 is connected to the referencevoltage terminal (ground terminal) of 0 V. The gate of MOSFET 101 isconnected to receive voltage Vin corresponding to programming data Din,and the control gates of four cell transistors MC1 to MC4 are connectedto receive selection voltages VG1 to VG4, respectively.

[0086]FIG. 20 is a pattern plan view of the circuit of FIG. 19 which isintegrated on a semiconductor wafer. The pattern is formed in and onsemiconductor substrate 102. Diffusion regions 103-1 to 103-6 are formedin the main surface area of semiconductor substrate 102 to constitutethe source and drain regions of MOSFET 101 and four cell transistors MC1to MC4. MOSFET 101 has gate 104 formed on a first insulation layer (notshown) formed on that part of semiconductor substrate 102 which liesbetween diffusion regions 103-1 and 103-2. Further, floating gates 105-1to 105-4 of cell transistors MC1 to MC4 are formed on the firstinsulation layer and over those portions of semiconductor substrate 102which lie between diffusion regions 103-2 and 103-3; 103-3 and 103-4;103-4 and 103-5; and 103-5 and 103-6. Control gates 106-1 to 106-4 ofcell transistors MC1 to MC4 are formed on a second insulation layer (notshown) and over floating gates 105-1 to 105-4.

[0087] With the memory cell of this construction, one end of seriescircuit 100 or a connection node between cell transistor MC1 andprogramming voltage applying MOSFET 101 is connected to column line (notshown) via a contact portion. Therefore, in the FIG. 19 circuit, it isonly necessary to form a single contact portion for four celltransistors. For this reason, the number of contact portions can bereduced in comparison with the conventional memory device, and the areaof the contact portions can be reduced in the case of forming a memorydevice of large capacity. When these memory cells are arranged in amatrix form, a selection transistor which is similar to the selectiontransistor ST in FIG. 10 is necessary. In this case, five transistorsare used to form a memory cell which is include four cell transistorsMC1 to MC4 and one selection transistor. That is, the number oftransistors used increases by one in comparison with the prior art case,but if the number of series-connected cell transistors MC is increased,then increase in the pattern area due to the use of the selectiontransistor can be made smaller than that of the pattern area due toformation of the contact portions.

[0088] In the memory device according to the second embodiment of thisinvention, a plurality of cell transistors are serially connected toreduce the number of contact portions. Therefore, unlike theconventional UVEPROM having a plurality of cell transistors connected inparallel, it is impossible to use a method of programming data byinjecting into the floating gate, electrons which are generated byimpact ionization occurring near the drain when a high voltage isapplied to the gate and drain of the cell transistor to cause a channelcurrent. That is, in the memory device of this invention, a differentmethod is used in which data is programmed by removing electrons fromthe floating gate or injecting holes into the floating gate to therebyset the threshold voltage negative.

[0089]FIG. 27 shows a circuit model in which the drain of MOSFET 120 isconnected to voltage source VD through load circuit 121, and the sourcethereof is connected to the ground terminal. If control gate voltage VGof MOSFET 120 is set to 0 V and voltage VD is set at a high voltagelevel to cause breakdown near the drain of MOSFET 120, electrons areemitted from the floating gate to set the threshold voltage of MOSFET120 negative.

[0090]FIG. 28 is a characteristic diagram showing the voltage-currentcharacteristic of floating gate type MOSFET. Characteristic curve 122 inthe drawing shows the characteristic prior to occurrence of thebreakdown, and in this case, drain current ID does not flow until thecontrol gate voltage becomes higher than a preset positive voltage. Incontrast, characteristic curve 123 shows the characteristic afteroccurrence of the breakdown, and in this case, drain current ID flowseven when control gate voltage VG is negative. That is, after thebreakdown has occurred in the circuit of FIG. 27, MOSFET 120 comes tohave characteristic curve 123 and the threshold voltage is changed froma positive value to a negative value. Further, even in a case where thebreakdown does not occur, and if punchthrough current flows, forexample, when control gate voltage VG is low, the threshold voltage ofMOSFET 120 may be changed to a negative value. An electric field betweenthe drain and the floating gate of MOSFET 120 has an important function,and part of holes generated by the breakdown or punchthrough occurringnear the drain is attracted by an electric field between the drain andthe floating gate and is injected into the floating gate. Thus, thefloating gate may be charged to be positive, making the thresholdvoltage negative. In the second embodiment, it is important to lowercontrol gate voltage VG, and holes can be injected into the floatinggate because of use of low control gate voltage VG. With the use ofpatterns shown in FIGS. 21A, 21B, 22 to 25, 26A and 26B, breakdown willoccur prior to punchthrough because of formation of high impurityconcentration region 112-1, 112-2 or 112.

[0091] There will now be described an operation of the circuit of FIG.19 with reference to FIGS. 29 and 30.

[0092]FIG. 29 shows a timing chart of the data programming, and in thisexample, data is programmed in cell transistor MC3 in period T1 and datais programmed in cell transistor MC2 in period T2. In period T1,selection voltages VG1, VG2 and VG4 are set to a high voltage level andselection voltage VG3 is set to a low voltage level of, for example, 0V. Then, gate voltage Vin of MOSFET 101 is set to a high voltage to turnon MOSF 101, permitting a high voltage of Vpp to be applied to one endof series circuit 100. Further, in series circuit 100, cell transistorsMC1, MC2 and MC4 are turned on and cell transistor MC3 is turned off,and therefore a high voltage is applied to the drain of cell transistorMC3 which is in the off state. At this time, if Vpp and vin are set tosuch values that breakdown or punchthrough may occur near the drain ofcell transistor MC3, then breakdown or punchthrough occurs in celltransistor MC3. Since control gate voltage VG3 of cell transistor MC3 isset at 0 V, holes generated by the breakdown or punchthrough areinjected into the floating gate. As a result, the threshold voltage ofcell transistor MC3 is changed to a negative value, thus programmingdata in cell transistor MC3.

[0093] In period T2, selection Voltages VG1, VG3 and VG4 are set to ahigh voltage level and only selection voltage VG2 is set to a lowvoltage level of 0 V. At this time, gate voltage Vin of MOSFET 101 iskept at a high voltage. In this condition, breakdown or punchthroughwill occur near the drain of cell transistor MC3, and then holesgenerated by the breakdown or punchthrough are injected into thefloating gate, thus programming data in cell transistor MC3.

[0094] In general, it is well known that avalanche breakdown occurringnear the drain is caused at a lower drain voltage when the gate voltageis set at a lower voltage. Therefore, the breakdown will occur when thecontrol gate voltage is set at 0 V and will not occur when it is set ata high voltage level.

[0095]FIG. 30 shows a timing chart at the time of data readout, and inthis example, data is sequentially read out from cell transistor MC1 tocell transistor MC4. In the data readout mode, a readout voltage lowerthan 5 V is applied to one end of series circuit 100 by a load circuit(not shown). Then, control gate voltage VG of a nonselected celltransistor is set to a high voltage of, for example, 5 V, and controlgate voltage VG of a selected cell transistor is set to a low voltageof, for example, 0 V. First, control gate voltage VG1 of cell transistorMC1 is set to 0 V and thus cell transistor MC1 is selected. If, forexample, data is not programmed in cell transistor MC1 and the thresholdvoltage thereof is positive, then cell transistor MC1 is kept off.Therefore, no current flows in series circuit 100.

[0096] Next, control gate voltage VG2 of cell transistor MC2 is set to 0V, and thus cell transistor MC2 is selected. If, for example, data isprogrammed in cell transistor MC2 and the threshold voltage thereof isnegative, then cell transistor MC2 is turned on. Since, at this time,control gate voltages VG1, VG3 and VG4 of cell transistors MC1, MC3 andMC4 are set at a high voltage level, cell transistors MC1, MC3 and MC4are all set in the conductive state. Therefore, current flows throughseries circuit 100. After this, control gate voltages VG3 and VG4 ofcell transistors MC3 and MC4 are sequentially set to 0 V.

[0097] In the data readout operation, potential at one end of seriescircuit 100 varies according to the ON and OFF states of selected celltransistor MC, and data can be determined by detecting the potentialvariation by a sense amplifier or the like.

[0098]FIG. 31 is a circuit diagram showing a UVEPROM of plural-bitoutput construction according to another embodiment of this invention.The UVEPROM includes row decoder 131, column decoder 132 and m memoryblocks 133-1 to 133-m. Each memory block 133 is formed with the sameconstruction as memory block 133-1. That is, in each memory block 133, aplurality of series circuits 100 constructed by serially connecting nfloating gate type cell transistors MC1 to MCn each having a controlgate and a floating gate are arranged on rows and columns. Each ofseries circuits 100 is connected at one end to a corresponding one ofcolumn lines Cl to Cp through E-type MOSFET 134. The gates of MOSFETs134 connected to series circuits 100 are respectively connected to rowlines X1, X2, . . . to which decoded outputs of row decoder 131 commonlyused for all memory blocks 133 are supplied, and the control gates ofcell transistors MC1 to MCn in each series circuit 100 are connected torow lines W11, W12, . . . , W1n, W21, W22, W2n, . . . to which decodedoutputs of row decoder 131 are supplied. Column lines Cl to Cp areconnected commonly to data programming/readout node 136 throughrespective column selection E-type MOSFETs 32 whose gates are connectedto column selection lines CSl to CSp supplied with respective decodedoutputs from column decoder 132 which is commonly used for all memoryblocks 133.

[0099] Node 136 is connected programming voltage source Vpp throughprogramming voltage applying E-type N-channel MOSFET 137 correspondingto MOSFET 101 in FIG. 19. Data input circuit 138 generates voltage vinaccording to the programming data. Node 136 is also connected to datadetection node 140 through potential isolation E-type MOSFET 139 whosegate is connected to receive preset bias voltage Vb. Data detection node140 is connected to the drain and gate of E-type P-channel load MOSFET141 whose source is connected to readout voltage source Vcc. Further,detection node 140 is connected to the input terminal of sense amplifier142 which determines is readout data and supplies this readout data tooutput buffer 143.

[0100] With the memory device of the above construction, it is onlynecessary to connect MOSFET 134 to column line C for every n celltransistors, and therefore it is possible to considerably reduce thenumber of contact portions required for connecting the memory cells tothe column lines. As a result, the area occupied by the contact portionscan be reduced, and the chip size for large memory capacity can beconsiderably reduced, thus lowering the manufacturing cost.

[0101] Now, the operation of the above memory device is explained.

[0102]FIG. 32 is a timing chart showing one example of data programmingoperation in the memory device. In this example, series circuit 100connected to row lines X1, W11 to W1n and column line C1 is selected anddata is programmed in the cell transistors of selected series circuit100. In this case, only column selection line CS1 is set to a highvoltage level by decoded outputs from column decoder 132 to turn oncolumn selection MOSFET 135-1 connected to column line C1. At this time,other column selection lines CS2 to CSp are all set to a low voltagelevel, and the remaining column selection MOSFETs 135-2 to 135-pconnected to column lines C2 to Cp are turned off. Further, only rowline X1 among row lines X1, X2, . . . is set to a high voltage level bydecoded outputs of row decoder 131, and series circuit selection MOSFETs134 which are connected to series circuits 100 arranged on the same roware turned on. Then, only row line Wil is set to a low voltage level bydecoded outputs of row decoder 131. At this time, if output voltage Vinof data input circuit 138 is set at a high voltage level, MOSFET 137 isturned on to permit high programming voltage Vpp to be applied to node136. The high voltage applied to node 136 is applied to column line C1through column selection MOSFET 135-1 which is set in the conductivestate. As a result, the breakdown will occur near the drain of celltransistor MC1 of selected series circuit 100 and holes are injectedinto the floating gate thereof, thus programming data in the celltransistor.

[0103] After this, only row line W12 is set to a low voltage level bydecoded outputs of row decoder 131. At this time, if output voltage vinof data input circuit 138 is set at a low voltage level, no hole isinjected into the floating gate of memory cell MC2 connected to row lineW12. The control gate voltage of the cell transistor in which no hole isinjected is set at a low voltage level. This is because row lines X andW are commonly used for all memory blocks 133 and it may becomenecessary to inject holes into the floating gate of a corresponding celltransistor in each of other memory blocks.

[0104] Then, the remaining row lines are sequentially set to a lowvoltage and voltage Vin is set to a voltage level corresponding to theprogramming data in the same manner as described above. Thus, data canbe programmed in n cell transistors of selected series circuit 100.

[0105] At this time, in order to prevent the breakdown from occurring inthe series circuits on the nonselected rows, it is necessary to decidethe impurity concentration of the drain region in each MOSFET 134 so asto set the starting voltage of the avalanche breakdown caused by anelectric field between the gate and drain higher than that of the memorycell.

[0106]FIG. 33 is a timing chart of different voltage waveforms ofsignals on row lines W11 to W1n in the data programming operation. Inthe timing chart of FIG. 32, the row line is normally set at a highvoltage level and set at a low voltage level for a preset period of timewhen data is programmed in the selected cell transistor. However, inthis example, row lines W1n to W11 are sequentially set to a low voltagelevel in this order, thus causing holes to be injected in the order fromcell transistor MCn to cell transistor MC1.

[0107] Further, in the operation shown by the timing chart of FIG. 32,the row line is normally set at a high voltage level, for example, 20 V,and is set at a low voltage level, for example, 0 V for a preset periodof time in the data programming mode. Fowever, it is possible to set therow lines at a voltage, for example, 5 V which is lower than 20 V whenno cell transistor is selected as shown by the timing chart of FIG. 34,thus reducing the voltage stress on the cell transistors.

[0108] In the readout operation in the memory device of FIG. 31, one ofrow lines X1, X2, . . . connected to the selected cell transistor is setto a high voltage level of, for example, 5 V, and one of row lines W11,W12, W13, . . . , W1n, W21, W22, W23, . . . , W2n, . . . connected tothe selected cell transistor is set to a low voltage level. Theremaining row lines are all set to the high voltage level, and celltransistors connected to the remaining row lines are all turned on. Atthis time, the selection cell transistors connected to the row lines setat the low voltage level are turned on or off according to the thresholdvoltages thereof. Then, node 140 is kept charged by means of MOSFET 141or is discharged according to the conduction state of the selection celltransistor. The potential variation on the node 140 is detected by meansof sense amplifier 142 which in turn supplies an output as readout datato the external through output buffer 143.

[0109]FIG. 35 is a circuit diagram showing the detail construction of adecoding section used in row decoder 131 of the memory device of FIG. 31to set the voltage of row line X1. In this example, six bit-signals A0to A5 are supplied as address signals, four series circuits 100 areprovided for each column line C, and each series circuit 100 isconstituted by 16 cell transistors.

[0110] The decoding section for setting the voltage of row line X1 isconnected to receive address signals A4 and A5. When both addresssignals are set at “1”, N-channel MOSFETs 151 and 152 are turned on sothat node 154 connected to voltage source Vcc through P-channel HOSFET153 which is normally set in the ON state may be set to “0”. As aresult, a signal on output node 158 of inverter 157 formed of P-channelMOSFET 155 and N-channel MOSFET 156 and connected to receive a signalfrom node 154 is set to “1”.

[0111] In the data programming mode, signal {overscore (PR)} is set at 0V and signal H is set at a high voltage level. Therefore, row line X1 ischarged by high voltage Vpp through N-channel MOSFET 159 and depletiontype (D-type) N-channel MOSFET 160. Since, at this time, the gate ofD-type N-channel HOSFET 161 connected between node 158 and row line X1is set at 0 V, no current will flow from row line X1 which is coupled tovoltage source Vpp towards node 158.

[0112] In the data readout mode, signal PR is set at 5 V, for example.Since, at this time, high voltage Vpp is not supplied, signal “1” onoutput node 158 of inverter 157 is transmitted as it is to row line X1.

[0113] In other decoding sections (not shown) for setting voltages ofother row lines X2, X3 and X4, combination signals of address signals A4and A5, address signals A4 and A5 and address signals A4 and A5 aresupplied to N-channel MOSFETs 151 and 152. When input address signalsare both set at “1”, a signal of high voltage level or “1” level issupplied from a corresponding row line.

[0114]FIG. 36 is a circuit diagram showing the detail construction of adecoding section used in row decoder 131 of FIG. 31 to set a voltage ofrow line wll. The decoder section is connected to receive addresssignals A0, A1, A2 and A3. When all the input addresses are set at “1”,N-channel MOSFETs 162, 163, 164 and 165 are turned on and node 167connected to voltage source Vcc through P-channel MOSFET 166 which isnormally set in the ON state is set to “0”. As a result, a signal onoutput node 171 of inverter 170 formed of P-channel MOSFET 168 andN-channel MOSFET 169 and connected to receive the signal on node 167 isset to “1”, and a signal on output node 175 of inverter 174 formed ofP-channel MOSFET 172 and N-channel MOSFET 173 and connected to receivethe signal on output node 171 of inverter 170 is set to “0” level.

[0115] In the data programming mode, signal PR is set at 0 V and signalH is set at a high voltage level. As a result, row line W11 is chargedthrough N-channel MOSFET 176 and D-type N-channel MOSFET 177 by highvoltage Vpp. Since, at this time, the signal on output node 175 ofinverter 174 is set at “0”, current flows from row line W11 towards node175 through D-type N-channel MOSFET 178, setting row line W11 to a lowvoltage level or 0 V. In contrast, when any one of address signals{overscore (A0)}, {overscore (A1)}, {overscore (A2)} and {overscore(A3)} is set at “0”, output node 175 of inverter 174 is set to “1”,thereby charging row line W11 by high voltage Vpp. That is, in the dataprogramming mode, row line W11 is set at 0 V at the time of selectionand at high voltage Vpp at the time of nonselection.

[0116] In the data readout mode, signal {overscore (PR)} is set at 5 V.Since, at this time, high voltage Vpp is not supplied, a signal onoutput node 175 of inverter 174 is supplied as it is to row line W11.

[0117] In other decoding sections (not shown) for setting voltage of rowlines W12, . . . and W110 to W116 (n-16), address signals A0 to A3 and{overscore (A0)} to {overscore (A3)} of a different combination aresupplied to the gates of N-channel MOSFETs 162, 163, 164 and 165. In thedata programming mode, when all the address signals are set at. “1”, anoutput voltage of 0 V is supplied from a corresponding row line.

[0118] The FIG. 36 circuit can be constituted to contain N-channelMOSFETs 179 and 180 and P-channel MOSFETs 181 and 182 which aresurrounded by broken lines in the drawing. Addition of the MOSFETscauses an output signal of “1” or “0” to be supplied through row linewil according to the logic levels of address signals A0 to A3 only whenaddress signals A4 and A5 are set to “1” to set row line X1 at “1”level. When row line X1 is not selected, that is, when row line X1 isset at “0”, row line W11 is always set at “0” so that a row lineconnected to a group of series-connected cell transistors which are notselected can be set at “0”, enhancing the reliability. However, if it isrequired to reduce the number of MOSFETs used, it is possible to omitthese MOSFETS.

[0119] In the FIG. 36 circuit, when row line W11 is selected in the dataprogramming mode, the voltage thereof is set at 0 V. In a case wheredata is programmed by causing breakdown, no problem will occur, but itis preferable to set the voltage to approx. 1 V when data programming iseffected by causing punch-through. In this case, as shown in FIG. 37,bias circuit 183 is connected between MOSFET 173 of inverter 174 in FIG.36 and the ground terminal, and the source voltage of N-channel MOSFET173 may be set to the threshold voltage of a cell transistor which isnot programmed, for example, 1 V. Bias circuit 183 can be constituted byan N-channel MOSFET whose gate and drain are connected together as shownin FIG. 37.

[0120] Further, use of the circuit of FIG. 37 increases current flowingin a cell transistor which is turned on in the data readout mode,enlarging the readout margin.

[0121]FIG. 38 is a diagram showing the truth values corresponding to theoutput states of row decoder 131 which generates output signals of thewaveforms shown in FIG. 32. Programming signal PR is set at “0” in thedata readout mode. One of 16 row lines W11 to W116 is set to “0”according to variation in address signals A0 to A3. Row decoder 131 canbe formed only to satisfy the output condition set up by the truthvalues.

[0122]FIG. 39 is a diagram showing the truth table corresponding to theoutput states of row decoder 131 which generates output signals of thewaveforms shown in FIG. 33 in the data programming mode. 16 row lineswll to W116 are sequentially set to 0 V in the order from W116 to W11according to variation in address signals A0 to A3. Row decoder 131 canbe formed only to satisfy the condition determined by the truth table.At this time, the readout or data programming mode is determined basedon signal PR, and when signal PR is at “0” indicating the readout mode,row decoder 131 is constituted to satisfy the truth table conditionshown in FIG. 38.

[0123]FIG. 40 is a circuit diagram showing the modified construction ofthe circuit shown in FIG. 19. In the memory device of the FIG. 19embodiment, the other end of each series circuit 100 or the source ofcell transistor MCn is connected to the ground terminal. In contrast, inthe memory device of the FIG. 40 embodiment, the other end of eachseries circuit 100 is connected to the ground terminal through MOSFET190 having a gate connected to signal line {overscore (PR)} which is setat a low voltage level in the data programming mode. With thisconstruction, substantially no current flows through series circuit 100in the data programming mode, and thus the drain voltage of the celltransistor can be prevented from being lowered. Therefore, holes can beefficiently injected into the floating gate thereof. MOSFET 190 can beprovided for each series circuit 100, but it is also possible to providea single MOSFET 190 commonly for a plurality of series circuits 100.

[0124] According to the second embodiment described above, a nonvolatilesemiconductor memory device can be obtained in which the chip size canbe reduced by reducing the number of contact holes and the manufacturingcost can be lowered.

[0125] However, since cell transistors are connected in series in theUVEPROM shown in FIG. 19, current flowing in each cell transistorbecomes small in comparison with the conventional UVEPROH.

[0126] The operation speed of reading out data from the cell transistordepends on current flowing in the cell transistor, and data readoutspeed increases as the cell current increases. Since data is read outform the cell transistor by detecting a potential at one end of theseries circuit 100 of cell transistors by use of a sense amplifiercircuit, it becomes important to charge or discharge one end of theseries circuit 100 as quickly as possible in order to enhance the datareadout speed. For example, if the channel width and channel length areset to W and L, respectively, current flowing in one cell transistorvaries in proportion to W/L. In a case where series circuit 100 isformed of four cell transistors as shown in FIG. 19, current which canflow in series circuit 100 is equal to or less than one-fourth thecurrent flowing in each cell transistor.

[0127] For this reason, it is preferable to lower the threshold voltageof each cell transistor in the UVEPROM of FIG. 19 in order to enhancethe readout speed. That is, the memory cell current becomes larger asthe threshold voltage becomes lower, and the data readout speed becomeshigher. In general, in order to lower the threshold voltage, theimpurity concentration of the channel region will be lowered. However,in order to lower the breakdown voltage and improve the programmingcharacteristics, it is necessary to increase the impurity concentrationof the channel region. That is, when the impurity concentration of thechannel region is high, the breakdown will occur at a lower voltage.Therefore, if the impurity concentration of the channel region islowered to enhance the data readout speed, the breakdown voltage becomeshigh and the programming characteristics will be deteriorated.

[0128] As described above, the impurity concentration of the channelregion in the cell transistor is an important factor for bothcharacteristics, the data readout speed and programming characteristics.That is, the two characteristics may be improved and deteriorated, orvice versa when the impurity concentration is set low or high,respectively. Therefore, it is necessary to make a compromise betweenthe two characteristics.

[0129] For the reasons described above, in the patterns of FIGS. 21A, 23to 25, and 26A, part of the channel region which is formed in contactwith the drain region has a higher impurity concentration than the otherregions.

[0130] Since part of the channel region is formed to have a higherimpurity concentration than the other regions, a breakdown may easilyoccur between the high impurity concentration region and the drainregion, thus lowering the breakdown voltage. Since, in this case, theother part of the channel region can be formed to have a sufficientlylow impurity concentration, the threshold voltage can be set at a lowvoltage, permitting a sufficiently large memory cell current. Further,impurity concentration of the portion other than the high impurityconcentration region is set to such a low value that each celltransistor can have a low threshold voltage and may permit asufficiently large channel current flow.

[0131] The same portions in FIG. 21A as those in FIG. 20 are denoted bythe same reference numerals. High impurity concentration regions 112-1and 112-2 are formed in those portions of channel region 111 which liein contact with field portions 110-1 and 110-2. FIG. 21B is a crosssectional view of a semiconductor device taken along line Z-Z, of thepattern of FIG. 21A. The semiconductor device has P-type substrate 102and floating gate 105-4 formed on insulation layer 108 which in turn isformed on substrate 102. Further, control gate 106-4 is formed oninsulation layer 109 which in turn is formed on floating gate 105-4. Forexample, floating gate 105-4 is formed of polycrystalline silicon, andcontrol gate 106-4 is formed of polycrystalline silicon or metal. Highimpurity concentration regions 112-1 and 112-2 containing, at a highimpurity concentration, P-type impurity which is the same as that of thesubstrate are formed in channel region 111 which is divided by means ofthe field portions 110-1 and 110-2 of insulation films 108 and 109.

[0132] With the above construction, a breakdown may easily occur betweenthe drain region and high impurity concentration 112-1 and 112-2 of eachchannel region 111, and thus the breakdown voltage can be lowered.Further, since portion of channel region 111 other than high impurityconcentration regions 112-1 and 112-2 is formed to have a low impurityconcentration and the threshold voltage is set to a low voltage, achannel current flowing each cell transistor can be increased. As aresult, both of the data readout speed and programming characteristicsin the memory device of this embodiment can be enhanced at the sametime.

[0133] In the memory device described above, high impurity concentrationregions 112-1 and 112-2 are formed in two portions of channel region 111in contact with the opposite field portions 110-1 and 110-2 ofinsulation layer 108. This is because misalignment will occur when anion-implantation mask is formed. That is, when the mask is formed,patterns surrounded by broken lines are first formed on an ion shieldingmember (not shown) so as to expose ion-implanted regions as shown in thepattern plan view of FIG. 22. Then, portion of the shielding memberexcept those on which the patterns are formed is removed. That is,portions 113 and 114 of the shielding member surrounded by broken linesas shown in FIG. 22 are removed to form the ion-implantation mask. Inthis case, even if the pattern is deviated on the shield memberrightwards or leftwards in the drawing, the total contact area betweenthe drain region and high impurity concentration region 125 formed inthe following step can be kept constant. As a result, variation inchannel current can be suppressed in this embodiment.

[0134] The breakdown between the drain region and high impurityconcentration regions 112-1 and 112-2 occurs in the form of junctionbreakdown when the impurity concentration of high impurity concentrationregions 112-1 and 112-2 are set extremely high, the operation thereofcannot be controlled by the gate potential. Therefore, it is necessaryto set the impurity concentration of high impurity concentration regions112-1 and 112-2 in such a range that the gate control can be madeeffective. That is, it is sufficient to ion-implant impurity at animpurity concentration slightly higher than that of the channel regioninto which impurity is ion-implanted to control the threshold voltage.As is well known in the art, a breakdown is caused by an electric fieldbetween the gate and drain of an ordinary MOSFET in a portion directlyunder the drain region thereof at a voltage lower than that at which thebreakdown occurs in an ordinary PN junction. The breakdown voltagebecomes high as the gate voltage becomes high, and the same breakdown asthe junction breakdown occurs when the gate voltage has reached acertain high voltage level. Therefore, it is preferable to set theimpurity concentration of high impurity concentration regions 112-1 and112-2 in such a range that the breakdown voltage can be controlled bythe gate voltage.

[0135] FIGS. 23 to 25, and 26A and 26B show other pattern plan views ofseries circuit 100 shown in FIG. 19.

[0136] In the pattern of FIG. 23, a high impurity concentration regioncorresponding to high impurity concentration regions 112-1 and 112-2shown in FIGS. 21A and 21B is formed on the entire portion of channelregion 111 which is positioned in contact with the drain regions 103-2to 103-5. That is, high impurity concentration region 112A is formed incontact with drain region 103-2. Likewise, high impurity concentrationregions 112B to 112D are formed in contact with drain regions 103-3 to103-5.

[0137] In the pattern of FIG. 24, high impurity concentration regions112-1 and 112-2 are formed in two portions of channel region 111 whichare positioned in contact with the drain region and the field insulationlayer.

[0138] In the pattern of FIG. 25, high impurity concentration region 112is formed only at the center of that portion of channel region ill whichis positioned in contact with the drain region.

[0139] In the pattern of FIG. 26A, high impurity concentration region112 is formed only at the center of that portion of channel region 111which is positioned in contact with the drain region, and it is formedin a triangle form. In a case where high impurity concentration region112 is formed in a triangle form, part of a pattern shown by brokenlines in FIG. 26B can be used as a pattern for forming theion-implantation mask, making it easy to form the mask.

[0140] A process of ion-implanting impurity into the channel region tocontrol the threshold voltage can be omitted by suitably setting theimpurity concentration of the semiconductor wafer on which the abovememory cell is formed. Therefore, it is only necessary to ion-implantingimpurity into channel region 111 to form high impurity concentrationregions 112-1, 112-2,and 112. For example, in a case where the memorydevice is formed on the semiconductor wafer having the substrateresistivity of 10 Ω·cm, a threshold voltage of approx. 0 V can beobtained without ion-implanting impurity into the channel region. It ispreferable that a cell transistor in which data is not programmed isturned off when it is selected and permits a larger current to flow whenit is not selected. For this reason, it is preferable to set thethreshold voltage to approx. 0 V.

[0141] In a UVEPROM having series-connected memory cells and formed withthe above pattern structure, the data readout speed and programmingcharacteristic can be enhanced to a satisfactory degree.

What is claimed is:
 1. A nonvolatile semiconductor memory devicecomprising: a plurality of cell transistors each of which includes acontrol gate and a floating gate and whose current paths are seriallyconnected to form a series circuit; selection means for selecting one ofcell transistors of said series circuit; and data programming meansconnected to one end of said series circuit, and for applying aprogramming voltage corresponding to programming data to one end of thecurrent path of said cell transistor selected by said selection means,and in an operation of data programming into said cell transistor, saiddata programming means applying a programming voltage to one end of thecurrent path of said cell transistor selected by said selection means,thereby emitting the electrons from the floating gate of said selectedcell transistor to said one end of the current path thereof or injectingholes from said one end of the current path into the floating gate ofsaid selected cell transistor.
 2. A nonvolatile semiconductor memorydevice according to claim 1, wherein said data programming means injectselectrons into the floating gate of said cell transistors and thenapplies a programming voltage to said one end of the current path ofsaid cell transistor selected according to the programming data by saidselection means, thereby emitting the electrons from the floating gateof said selected cell transistor to said one end of the current paththereof or injecting holes from said one end of the current path intothe floating gate of said selected cell transistor in the operation modeof data programming into said cell transistors.
 3. A nonvolatilesemiconductor memory device according to claim 1 or 2, furthercomprising data readout means connected to one end of said seriescircuit and for reading out data stored in said selected cell transistoraccording to whether or not current flows from the one end to the otherend of said series circuit.
 4. A nonvolatile semiconductor memory deviceaccording to claim 1 or 2, further comprising a transistor connected atone end to the other end of said series circuit and connected at theother end to a reference voltage, said transistor being turned off whendata is programmed into said cell transistor by means of said dataprogramming means.
 5. A nonvolatile semiconductor memory deviceaccording to claim 1 or 2, wherein said selection means includes a rowdecoder.
 6. A nonvolatile semiconductor memory device according to claim5, which further comprises voltage generating means for generating afirst voltage and a second programming voltage higher than the firstvoltage, and in which an output voltage of said voltage generating meansis supplied as a power source voltage to said row decoder.
 7. Anonvolatile semiconductor memory device according to claim 1 or 2,wherein said data programming means includes data input means forgenerating first and second output signals according to programming dataand a signal specifying the programming mode; first switching meanswhose conduction state is controlled by the first output signal of saiddata input means so as to permit the programming voltage to beselectively supplied to the one end of said series circuit; and secondswitching means whose conduction state is controlled by the secondoutput signal of said data input means so as to permit the referencevoltage to be applied to the other end of said series circuit.
 8. Anonvolatile semiconductor memory device according to claim 1 or 2,further comprising data readout means which includes switching meansconnected at one end to one end of said series circuit and connected tobe turned off in the data programming mode and turned on in the datareadout mode; load means connected to the other end of said switchingmeans; and data detection means connected to the other end of saidswitching means.
 9. A nonvolatile semiconductor memory device accordingto claim 1 or 2, further comprising a memory array constituted by aplurality of said series circuits arranged in matrix form; selectiontransistors for selecting a row or rows of said series circuits of saidmemory array; column selection transistors for selecting a column orcolumns of said memory array; and a column decoder for selectivelycontrolling the conduction states of said column selection transistors.10. A nonvolatile semiconductor memory device according to claim 9,further comprising array dividing transistors for dividing said memoryarray into a plurality of blocks; and block specifying column decoderfor selectively controlling the conduction states of said array dividingtransistors, thus specifying the memory block in which data isprogrammed or from which data is read out.
 11. A nonvolatilesemiconductor memory device according to claim 1 or 2, wherein said celltransistors each includes a MOSFET in which data is programmed or erasedby the tunnel effect.
 12. A nonvolatile semiconductor memory deviceaccording to claim 11, wherein said MOSFET includes an insulation filmwhich is formed between the floating gate and a substrate and which hasa thin film portion formed thinner than the other film portion.
 13. Anonvolatile semiconductor memory device according to claim 1 or 2,wherein said cell transistors each include a MOSFET in which data iselectrically programmed by breakdown occurring near a drain thereof orpunchthrough.
 14. A nonvolatile semiconductor memory device according toclaim 13, wherein said MOSFET includes a high impurity concentrationregion or regions formed in that part of a channel region which is incontact with the drain region, having the same conductivity type as thatof the channel region and formed to have a higher impurity concentrationthan the channel region.
 15. A nonvolatile semiconductor memory deviceaccording to claim 11, wherein each of said cell transistors has a gateinsulation film formed between said floating gate and channel region andhaving such a thickness as to cause the tunnel effect.
 16. A nonvolatilesemiconductor memory device according to claim 13, wherein dataprogrammed in said cell transistors can be erased by applyingultraviolet rays.
 17. A nonvolatile semiconductor memory deviceaccording to claim 1 or 2, wherein data programming into saidseries-connected cell transistors is sequentially effected starting fromthat one of said cell transistors which is connected to the other end ofsaid series circuit.
 18. A nonvolatile semiconductor memory deviceaccording to claim 1 or 2, wherein said programming means includes alatch circuit for latching programming data and effects the operation ofdata programming into said cell transistor according to data latched insaid latch circuit.
 19. A nonvolatile semiconductor memory deviceaccording to claim 18, wherein said programming means includes boostermeans for stepping up a voltage at said one end of said series circuitbased on data latched in said latch circuit.
 20. A nonvolatilesemiconductor memory device according to claim 9, wherein saidprogramming means includes a latch circuit for latching programming datafor each column of said memory cell array, and effects the operation ofdata programming into said cell transistors based on the latched data.21. A nonvolatile semiconductor memory device according to claim 20,wherein said programming means includes booster means for stepping up avoltage at said one end of said series circuit based on data latched insaid latch circuit, thereby causing electrons to be emitted from saidfloating gate.
 22. A nonvolatile semiconductor memory device accordingto claim 1 or 2, further comprising a cell array having said seriescircuits arranged in a matrix form and in which said programming meansincludes means for applying a high voltage to a selected one column ofsaid cell array based on programming data to emit electrons from saidfloating gate and applying a voltage between said high voltage and 0 Vto the remaining columns.
 23. A nonvolatile semiconductor memory deviceaccording to claim 1 or 2, wherein said programming means selectivelyapplies first and second voltages higher than 0 V to said one end ofsaid series circuit, the first voltage being set higher than the secondvoltage and electrons being emitted from said floating gate when thefirst voltage is applied to said one end of said series circuit.
 24. Anonvolatile semiconductor memory device according to claim 9, whereinthe gates of said cell transistors which belong to unselected rows areset at the logic 0 in read operation.
 25. A nonvolatile semiconductormemory device according to claim 1 or 2, wherein a voltage betweenprogramming voltage and 0 V is applied to the control gates of said celltransistors in a period of time in which none of said cell transistorsare selected.
 26. A nonvolatile semiconductor memory device according toclaim 9, further comprising array dividing transistors for dividing saidmemory array into a plurality of blocks, said dividing transistors whichare each connected at one end to the gate of each of said celltransistors in said memory block and is connected at the other end toreceive a signal generated based on a signal for selecting one of saidmemory blocks, and whose conduction state is controlled by a selectionsignal for controlling the conduction states of said selectiontransistors.